1. Field of the Invention
The present invention relates to a system, a method and a program for testing an integrated circuit, particularly for a complementary metal oxide semiconductor (CMOS) circuit.
2. Description of the Related Art
A CMOS circuit designed in such a way that no directs current path exists when there is no defect. Therefore, after an input is determined, only a minute amount of off-leakage current flows at a steady state. Therefore, a CMOS integrated circuit with a defective or faulty part causing an abnormal leakage current can be easily distinguished from a defect-free or fault-free one and rejected by measuring the power supply current values. Utilizing the phenomenon described above, a quiescent supply current (IDDQ) testing is a method of judging whether or not there is a defect or fault in the circuit, by measuring a quiescent supply current IDDQ which is a current in a quiescent state of an integrated circuit.
However, the miniaturization as a result of progress of fabrication process of integrated circuits, the IDDQ values have become in the range of 100 μA to tens of milli amperes or more in integrated circuits fabricated with a design rule of not more than approximately 0.25 μm. Therefore, in a pass/fail or not-faulty/faulty judging method for integrated circuits using a fixed specification value of quiescent supply current IDDQ, its value has to be in the range of several milli amperes to tens of milli amperes. For this reason, only the defects (faults) which generate abnormal currents of not less than several milli amperes can be detected, and hence the defect (fault) detection ability using the quiescent supply current testing has decreased greatly.
Therefore, there is a strong need for a quiescent supply current (IDDQ) test method in which attention is paid to measured values, average, deviation and outliers of the quiescent supply current IDDQ at a plurality of measurement points of an integrated circuit. There has been proposed a method of judging whether an integrated circuit is fault-free or not, by using ratio of each value to an average value of the values of the quiescent supply current IDDQ at a plurality of measurement points which are measured beforehand for fault-free reference samples of the integrated circuit, the measured values and an average value of the quiescent supply current IDDQ at a plurality of measurement points of the integrated circuit.
In general, the quiescent supply current IDDQ is obtained by adequately functionally operating the integrated circuit, by stopping the clock at an appropriate cycle (a measurement point), and by measuring after a lapse of an appropriate waiting time. In order to shorten the testing time, it is necessary to reduce the number of the measurement points to be as small as possible. It is a general practice to find out the measurement points by utilizing a dedicated measurement point selection tool, which receives connection information of the integrated circuit and sometimes adjacent wiring information extracted from connection information and layout information of the integrated circuit, and test patterns for the integrated circuit.
In the method disclosed in Japanese Patent Laid Open Publication No. 2001-91566, in a case where a measured value of quiescent supply current IDDQ of a fault-free reference (usually, an average value of measured values of quiescent supply current IDDQ of a plurality of references) is plotted as abscissa, and a measured value of quiescent supply current IDDQ of a fault-free integrated circuit is plotted as ordinate, it is supposed that all measurement points will be plotted on or near a straight line passing an origin. As shown in FIG. 11, criterion lines for judging fault-free products are set on both sides of a solid line, and along the solid line. When all the measurement points of the integrated circuit are included in a fault-free region sandwiched between the two criterion lines indicated by short dashed lines in FIG. 11, the integrated circuit is judged to be a fault-free or defect-free product. The marks “•” in FIG. 11 are IDDQ values of the fault-free product. A “reference” here refers to an integrated circuit that is manufactured by a process in which the process center condition is targeted.
Generally, in the mass production of integrated circuits however, process conditions often deviate from the targeted process center condition, and in particular, in fine processes of less than 0.25 μm, which are generally called deep sub-micron (DSM) processes, it becomes difficult to control the various process parameters and hence the deviation of process conditions tends to be great as the miniaturization advances. Thus, even in a relatively well-controlled production factory, the process often deviates from the center condition to some degree. As a result, when an integrated circuit is produced by accident under process conditions which deviate from the center condition, even in a fault-free integrated circuit, as shown in FIG. 11, for example, measurement points are roughly divided into two groups G1 and G2 as indicated by the symbol “+” and are plotted while falling outside of the preconditions of Japanese Patent Laid Open Publication No. 2001-91566. In this case, even if the straight line can be fitted to the measured values of the quiescent supply current IDDQ in one of the two groups, the measured values of quiescent supply current IDDQ in the other group always deviates from the straight line. For this reason, the product will be dealt with as a faulty (defective) product even if it is a fault-free (defect-free) one. This situation is apt to occur especially in a case where a few threshold voltages Vth,n and Vth,p of an NMOS and a PMOS are used for each circuit block of an integrated circuit for the purpose of increasing operational speed or the like.
In general, the number of integrated circuits manufactured under specific process conditions is large. Accordingly, many fault-free products are treated as faulty products, and integrated circuit manufacturers suffer a great loss. However, on the contrary, if the range of judging fault-free products is widened in fear of such a loss, it follows that faulty products are misjudged to be fault-free products and are shipped erroneously, and this might result in the loss of customer trust. Thus, in the test method of the quiescent supply current IDDQ disclosed in Japanese Patent Laid Open Publication No. 2001-91566, it has been difficult to make a high-reliability judgment on whether an integrated circuit is a fault-free (defect-free) or a faulty (defective) product, by appropriately adapting to dispersion in process conditions which are usually supposed in the fields of mass production. Then, practical use of this test method in actual fields of mass production of integrated circuit has been difficult.